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Browse Questions » STEP 7 / STEP 7 Lite: Want Towards Utilize M10.6 Alternatively M255 Automation System the Entry Req - Is there a program function to change the CPU clock memory to 10 or 255?

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STEP 7 / STEP 7 Lite: Want Towards Utilize M10.6 Alternatively M255 Automation System the Entry Req - Is there a program function to change the CPU clock memory to 10 or 255?

Good day guys,
please what can I do in the case of trying to use a different marker from what has been used in an existing program.
For example, i have an existing program which i want to incorporate a PUT-GET function into. The program has its Clock memory set at 0.
I want to use M10.6 or M255 as the input REQ whenever there is a positive edge. That would require that I change the CPU clock memory to 10 0r 255. Will there be any effect on the other program function in the program? How best can i achieve this?
Also, I want to set a Marker bit to be always ON or always OFF or to set a call for an FB in OB1 to serve as the EN, ENO and INIT_COM.
Please how can I do this? All the M0.0 to M0.7 have been used. I have attached a screenshot.
Thank you.
David
Piotr.M
Hi
The Clock Memory gives square wave. You configure it in HW Config.
To make pulses You need use positive / negative edge instructions:
Let's say Your clock bit is MB0 (M0.0 to M0.7)
Let's say Your clock pulses will be in MB1 (in same order as bits in MB0)
and MB2 (M2.0 to M2.7) would contain bits for exclusive use of edge detectors:
A M0.0
FP M2.0
= M1.0
A M0.1
FP M2.1
= M1.1
and so on to M0.7, M2.7, M1.7
This way You get wave and one shot pulses for every clock memory bit.
Note: When You need 50ms pulse use both edges of  100ms wave.
 
------------------------------------------------------------------------------------------
Split from
Clock pulse in Step 7-s300
.

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Answers(1)

## Siemens Self Support - Regarding Marker Usage & Clock Memory David, Changing the CPU clock memory (currently at 0) to utilize M10.6 or M255 as your PUT/GET REQ *will* likely impact existing program functions relying on the original clock memory configuration. **Best Approach:** Instead of altering the core clock memory, leverage positive/negative edge detection as Piotr.M detailed. Use your existing clock memory (MB0) to generate pulses in another memory bit (MB1 & MB2) for exclusive edge detection (FP instruction). This isolates the new functionality and avoids disrupting existing logic. **For constant ON/OFF markers or FB enable:** Utilize available markers outside the M0.0-M0.7 range (e.g., M10.0 for always ON, M10.1 for always OFF). For FB control (EN, ENO, INIT_COM), dedicate marker bits (e.g., M10.2 for EN) and implement the logic within OB1. **SiePortal Resources:** Refer to the Siemens Industry Online Support for detailed instructions on edge detection (FP instruction) and marker bit usage in STEP 7. Let me know if you'd like specific code examples for edge detection or FB control implementation.

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